United States Patent: 5,353,431 ( 10 of 13 ) United States Patent 5,353,431 Doyle , et al. October 4, 1994 Memory address decoder with storage for memory attribute information Abstract A programmable and testable memory address decoder for a computer system where a static random access memory device is used to store memory configuration information. The computer system includes a processor which is coupled to the memory address decoder via data and address lines. The memory address decoder includes an SRAM for storing a memory map which associates memory attributes with memory ranges or blocks of memory. The memory attributes include: memory residence, caching, write protection of memory ranges, and the decoding of other memory modules. The present invention also includes control logic, a read-back register, and a mode register for controlling the loading and read back verification of the SRAM. The control logic operates the memory address decoder in one of four modes. These modes include: 1) power-up mode, 2) programming mode, 3) read back mode, and 4) normal operation mode. One of these modes is selected by loading the mode register with a value corresponding to the desired mode. A default power up mode is entered after power is first applied to the computer system. When the processor specifies a programming mode, the processor may write data directly into the SRAM. When the processor specifies the read back mode, the contents of the SRAM may be read back by the processor through the read back register. A normal mode may be entered in order to enable access to system memory (DRAM) with memory attribute information. Inventors: Doyle; Patrick F. (Hillsboro, OR); Cross; Leonard W. (Beaverton, OR); Noar; Roger (Tigard, OR) Assignee: Intel Corporation (Santa Clara, CA) Appl. No.: 193516 Filed: February 8, 1994 Current U.S. Class:711/206; 711/144; 711/145; 711/202 Intern'l Class: G06F 012/02 Field of Search: 364/200 MS File,900 MS File 395/400,425 References Cited [Referenced By] U.S. Patent Documents 4701878Oct., 1987Gunkel et al.395/325. 4821182Apr., 1989Leininger395/425. 4905142Feb., 1990Matsubara et al.395/425. 4905184Feb., 1990Giridhar et al.395/400. Primary Examiner: Dixon; Joseph L. Assistant Examiner: Nguyen; Hiep T. Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman Parent Case Text This is a continuation of application Ser. No. 07/692,483 filed Apr. 29, 1991, now abandoned. Claims We claim: 1. An improved memory address decoder comprising: means for receiving addressing signals; memory means for storing a Software programmable memory map, said memory means coupled to said receiving means, said memory map for storing memory attribute information associated with said addressing signals received by said receiving means, said memory attribute information for defining at least one state of a plurality of memory attributes associated with a corresponding block of system memory indicated by said addressing signals; control logic coupled to said memory means for controlling access to said memory means and controlling an output of said memory attribute information from said memory means, said control logic further including means for programming said software programmable memory map according to at least one processor instruction; and means for outputting said memory attribute information, said means for outputting coupled to said memory means. 2. The improved memory address decoder as claimed in claim 1 further including means for reading the content of said memory means, said means for reading coupled to said memory means. 3. The improved memory address decoder as claimed in claim 2 wherein said means for reading further including a read-back register for storing the content of a location in said memory means while said location is being read. 4. The improved memory address decoder as claimed in claim 2 further including: means for receiving mode information; and a mode register coupled to said means for receiving mode information and said control logic, said mode register for storing mode information received by said means for receiving mode information, said mode information read by said control logic, said means for reading the contents of said memory means activated when said mode information indicates a read back mode. 5. The improved memory address decoder as claimed in claim 1 further including: means for receiving mode information; and a mode register coupled to said means for receiving mode information and said control logic, said mode register for storing mode information received by said means for receiving mode information, said mode information read by said control logic. 6. The improved memory address decoder as claimed in claim 5 wherein said control logic further includes means for disabling the output of said memory attribute information from said memory means, said means for disabling being activated when said mode information indicates a power-up mode. 7. The improved memory address decoder as claimed in claim 4 wherein said means for programming is activated when said mode information indicates a programming mode. 8. The improved memory address decoder as claimed in claim 5 wherein said control logic further includes means for enabling the output of said memory attribute information from said memory means, said means for enabling being activated when said mode information indicates a normal operation mode. 9. The improved memory address decoder as claimed in claim 1 further including non-volatile memory means for storing processing logic and memory configuration data. 10. The improved memory address decoder as claimed in claim 1 wherein said memory means is a static random access memory device. 11. The improved memory address decoder as claimed in claim 1 wherein said plurality of memory attributes includes memory residence information. 12. The improved memory address decoder as claimed in claim 1 wherein said plurality of memory attributes includes write protection information. 13. The improved memory address decoder as claimed in claim 1 wherein said plurality of memory attributes includes internal cache information. 14. The improved memory address decoder as claimed in claim 1 wherein said plurality of memory attributes includes external cache information. 15. The improved memory address decoder as claimed in claim 1 wherein said plurality of memory attributes includes memory module configuration information. 16. A process for decoding addressing signals, said process comprising the steps of: receiving addressing signals; accessing a software programmable memory map stored in a memory means, said memory map for storing memory attribute information associated with said addressing signals received in said receiving step, said memory attribute information for defining at least one state of a plurality of memory attributes associated with a corresponding block of system memory indicated by said addressing signals; reading a mode register to determine mode information; programming said software programmable memory map according to at least one processor instruction when said mode information indicates a programming mode; and outputting said memory attribute information when indicated by said mode information. 17. The process as claimed in claim 16 further including a step of reading the contents of said memory means when said mode information indicates a read-back mode. 18. The process as claimed in claim 16 further including a step of reading processing logic and memory configuration data stored in a non-volatile memory means. 19. The process as claimed in claim 16 wherein said accessing step further includes a step of reading memory residence information stored in said memory means. 20. The process as claimed in claim 16 wherein said accessing step further includes a step of reading write protection information stored in said memory means. 21. The process as claimed in claim 16 wherein said accessing step further includes a step of reading internal cache information stored in said memory means. 22. The process as claimed in claim 16 wherein said accessing step further includes a step of reading external cache information stored in said memory means. 23. The process as claimed in claim 16 wherein said accessing step further includes a step of reading memory module configuration information stored in said memory means. 24. The process as claimed in claim 16 wherein said outputting step further includes a step of disabling the output of said memory attribute information when said mode information indicates a power-up mode. 25. The process as claimed in claim 16 wherein said outputting step further includes a step of enabling the output of said memory attribute information when said mode information indicates a normal operation mode. Description FIELD OF THE INVENTION The present invention relates to computer systems. Specifically, the present invention relates to memory interface, decode and control mechanisms for use in a computer system. BACKGROUND OF THE INVENTION The increased speed of computers today and the increased complexity of the associated memory system requires increased performance, flexibility, automation, and testing ability in the system memory decoder. A memory system coupled to a typical computer system may have numerous system memory configurations of different size memory devices and a variety of memory attribute information including attributes associated with a central processing unit (CPU) internal cache, attributes associated with a CPU external cache, attributes associated with the write protection of particular segments of memory within the memory system, and a memory map for associating memory addresses with physical locations within the memory system. Other types of memory configuration information may be significant in other computer systems or as a particular computer system increases in complexity. Many prior art computer systems use switches or jumpers to define memory size, location, or other memory attributes. Clearly, switches or jumpers retain memory attribute definition even though the computer system loses power; however, switches and jumpers are inconvenient to configure and cannot be automatically configured. Further, configuring switches or jumpers typically requires access to a circuit board inside the computer system. Other computer systems dynamically determine their memory system configurations on power up initialization of the computer system. As memory systems get more complex, however, this procedure can be very time consuming. Other computer systems employ a non-volatile memory device for retaining memory configuration information. In this way, a manufacturer or user of the computer system does not need to manipulate a set of switches or jumpers and the computer system does not need to dynamically determine its configuration at power up initialization. Further, during normal operations of the computer system, the non-volatile memory configuration information can be rapidly accessed and used by the memory decoder or memory controller. Non-volatile memory, however, is not easily modified when the memory configuration of the computer system changes. Typically, the non-volatile memory device must be removed from a circuit board of the computer system and replaced with a non-volatile memory device containing an updated version of the memory configuration information. This replacement of a non-volatile memory device is time consuming, expensive, and likely to introduce other problems during the manipulation of the circuit board. Further, the non-volatile memory configuration information cannot be modified by the processing logic during operation of the computer system. Prior art systems do not provide a means for reading and verifying the content of a memory configuration storage means. A better method is needed for storing, manipulating, and verifying memory configuration information in a computer system. SUMMARY OF THE INVENTION The present invention is a programmable and testable memory address decoder for a computer system where a memory means is used for storing memory configuration information. The present invention includes means for verifying the contents of the static random access memory device. The computer system includes a processor which is coupled to the memory address decoder via data and address lines. The processor makes access to system memory, typically dynamic random access memory (DRAM) through the memory address decoder. The memory address decoder includes a memory means for storing system memory attribute information. In the preferred embodiment, the memory means is a static random access memory (SRAM). The SRAM stores a memory map which associates memory attributes with memory ranges or blocks of memory. The following memory attributes are among those that can be so associated: memory residence (on board or off board memory), the ability of the associated block of system memory to be cached (internal cache, external cache, or cache disabled), write protection of memory ranges, and the decoding of single in-line memory modules (SIMM). The SRAM uses only the most significant portion of the CPU address lines. Thus, the address presented to the SRAM corresponds to a range or block of system memory addresses. Each bit at a given memory address of the SRAM defines the state of a memory attribute associated with the corresponding block of system memory. The present invention also includes control logic, a read-back register, and a mode register for controlling the loading and read back verification of the SRAM. The memory address decoder also includes a non-volatile memory device which contains embedded firmware comprising processing logic and non-volatile data used for testing and programming the memory address decoder. The programming (i.e. loading) of the SRAM and read-back register is controlled by a state machine located within the control logic. The control logic operates the memory address decoder in one of four modes. These modes include: 1) power-up mode, 2) programming mode, 3) read back mode, and 4) normal operation mode. One of these modes is selected by loading the mode register with a value corresponding to the desired mode. The operation of the memory address decoder in each of these four modes is controlled by the control logic. Both the mode register and the read back register are coupled to an I/O bus. The processor of the computer system may access either the mode register or the read back register by issuing an I/O instruction with a distinct address associated with each of the registers. Two bits in the mode register specify one of four operating modes of the control logic. A default power up mode is entered after power is first applied to the computer system of the present invention. In power up mode, the control logic forces the SRAM into a high impedance output state and any special interpretation of CPU commands by the control logic is prevented. In power up mode, the SRAM is neither used as a decoder nor programmed by the control logic. Output of memory attribute information is disabled. After power up, a different mode may be entered after the processor loads the mode register with a value corresponding to one of the other available modes. When the processor loads the mode register with a value corresponding to a programming mode, the processor may write directly into the SRAM by performing a memory write operation. Data is presented to the SRAM via data lines through a buffer. The address of the SRAM location into which each data item is loaded is specified by the address lines. At the completion of each memory write cycle, the control logic generates a ready signal for the processor. The processor can thereafter set up for next memory write cycle. Memory write cycles may continue until the contents of the SRAM have been completely loaded. The processor specifies the read back mode by loading the corresponding bits into the mode register. The contents of the SRAM may then be read back by the processor through the read back register. Reading back the contents of the SRAM is a two step process. The processor first performs a memory write operation after specifying read back mode by loading the mode register. The read back register may then be read by the processor using an I/O instruction with an address corresponding to the I/O space address of the read back register. The entire contents of the SRAM may be verified by the processor using multiple memory write and I/O read cycles of the contents of the read back register for each address in the SRAM. The fourth mode of operation of the memory address decoder of the present invention, is the normal decoder operation mode. After the SRAM contents have been loaded and verified using programming and read back modes, a normal mode may